Symmetric Logic Synthesis with Phase Assignment

Details Symmetric Logic Synthesis with Phase Assignment Symmetric Logic Synthesis with Phase Assignment

2001-04-13

arxiv.org/abs/math/0104153v1

Mathematics

General Mathematics

7 pages; 22nd Information Theory Symposium (IEEE/Benelux, U-Twente, May 2001)

Scientific paper

Decomposition of any Boolean Function BF_n of n binary inputs into an optimal inverter coupled network of Symmetric Boolean functions SF_k (k \leq n) is described. Each SF component is implemented by Threshold Logic Cells, forming a complete and compact T-Cell Library. Optimal phase assignment of input polarities maximizes local symmetries. The "rank spectrum" is a new BF_n description independent of input ordering, obtained by mapping its minterms onto an othogonal n \times n grid of (transistor-) switched conductive paths, minimizing crossings in the silicon plane. Using this ortho-grid structure for the layout of SF_k cells, without mapping to T-cells, yields better area efficiency, exploiting the maximal logic path sharing in SF's. Results obtained with an optimization tool "Ortolog" based on these concepts, for very fast O(n^2) detecting and enhancing local symmetries of a BF_n, are reported. Relaxing symmetric- to planar- Boolean functions is sketched, to improve low- symmetry BF decomposition.

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