Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

Details Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

2009-09-12

arxiv.org/abs/0909.2369v1

Z. El. ALAOUI ISMAILI and A. MOUSSA, " Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA", Internatio

Computer Science

Cryptography and Security

International Journal of Computer Science Issues (IJCSI), Volume 1, pp33-40, August 2009

Scientific paper

This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication.

Affiliated with

Also associated with

No associations

Rating

Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.

If you have personal experience with Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFWR-SCP-O-628466