ReveR: Software Simulator of Reversible Processor with Stack

Details ReveR: Software Simulator of Reversible Processor with Stack ReveR: Software Simulator of Reversible Processor with Stack

2011-04-05

arxiv.org/abs/1104.0924v2

Computer Science

Emerging Technologies

LaTeX, 7 pages, no figures, 3 tables, v2: spelling and grammar corrected; project url http://friedmann.objectis.net/Members/vl

Scientific paper

A software model of a reversible processor ReveR with the stack is discussed
in this paper. An architecture, the minimal set of elementary reversible
operations together with an implementation of the basic control flow structures
and procedures calls using simple assembler language are described.

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