Refinement-based verification of sequential implementations of Stateflow charts

Details Refinement-based verification of sequential implementations of Stateflow charts Refinement-based verification of sequential implementations of Stateflow charts

Publishing date

2011-06-21

URL

arxiv.org/abs/1106.4094v1

Journals

EPTCS 55, 2011, pp. 65-83

Science

Computer Science

Field

Logic in Computer Science

Additional info

In Proceedings Refine 2011, arXiv:1106.3488

Type

Scientific paper

Digital Object Identifier

10.4204/EPTCS.55.5

Abstract

Simulink/Stateflow charts are widely used in industry for the specification of control systems, which are often safety-critical. This suggests a need for a formal treatment of such models. In previous work, we have proposed a technique for automatic generation of formal models of Stateflow blocks to support refinement-based reasoning. In this article, we present a refinement strategy that supports the verification of automatically generated sequential C implementations of Stateflow charts. In particular, we discuss how this strategy can be specialised to take advantage of architectural features in order to allow a higher level of automation.

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