Computer Science
Scientific paper
Jul 2000
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2000spie.4028..157h&link_type=abstract
Proc. SPIE Vol. 4028, p. 157-165, Infrared Detectors and Focal Plane Arrays VI, Eustace L. Dereniak; Robert E. Sampson; Eds.
Computer Science
Scientific paper
A 512 X 512 monolithic Platinum Silicide Schottky Barrier detector array with random line selectable operation was proposed. The device modified from an interline CCD configuration by adapt a Random Line selected Charge Accumulation charge-coupled device on the vertical register and four tap readout on the horizontal CCD register to achieve a high frame rate and high fill factor operation. A 9-bit digital decoder is used to select which line of the sensor array that transfer their signals to the vertical CCD register. Accompanied with the vertical reset drain circuitry, either one line or up to 512 lines of the video signals can be selected and transferred to the vertical CCD register. All of the video signals on the unselected lines are then transferred to the vertical CCD channel simultaneously and finally dumped to the vertical reset drain. Since this unique readout structure, a frame rate of up to 240 frames/second can be achieved for 128 X 128 of the SBD array under 5 MHz of clock frequency. A high-speed sub-frame readout format can be easily fulfilled under this architecture. This architecture not only maintains the advantages of line-addressed charge- accumulation structure but also provides the capability to readout any portion of the array.
Chang Chun-Yen
Horng Gwo-Ji
Wang Weng-Lyang
Yen Yung Chau
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