Process optimization of Si:As indium bumped focal plane arrays

Details Process optimization of Si:As indium bumped focal plane arrays Process optimization of Si:As indium bumped focal plane arrays

Jul 1992

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1992spie.1686...91b&link_type=abstract

In: Test and evaluation of IR detectors and arrays II; Proceedings of the Meeting, Orlando, FL, Apr. 22, 23, 1992 (A94-12744 02-

Computer Science

Performance

Component Reliability, Electrical Resistance, Focal Plane Devices, Hybrid Circuits, Thermal Stresses, Delaminating, Indium, Tensile Strength, Thermal Cycling Tests

Scientific paper

In a particular application, a Si:As focal plane array may experience many thermal cycles from ambient down to its operating temperature (10 Kelvin) at a very rapid cooldown rate. Aerojet Electronic Systems Division's task, under company funds, was to consistently produce focal plane arrays that could reliably survive this kind of thermal cycling with no degradation in performance or mechanical damage. Of utmost importance in the verification of the focal plane array reliability is the assurance that the test configuration reflects flight configuration in material, interfaces, and process procedures. Using flight-like hardware, process procedures were developed to optimize hybridization parameters (the means of bonding the indium bumped readout electronics to the detector array) with bonding strength and electrical resistance selected as the figures of merit. When the materials, processes and assembly procedures were developed, a final verification was conducted which consisted of rapidly thermal cycling two flight-like hybrids. The hybrids successfully withstood more than 800 cycles from 60 Kelvin to 10 Kelvin and over 20 cycles from 300 Kelvin to 60 Kelvin with no degradation in performance or mechanical integrity.

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