Mathematics – Logic
Scientific paper
Jan 1993
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1993phdt........19k&link_type=abstract
Ph.D. Thesis Technische Univ., Eindhoven (Netherlands). Electronic Design Group.
Mathematics
Logic
Computerized Simulation, Digital Electronics, Electronic Equipment, Mathematical Logic, Nonlinear Programming, Analog To Digital Converters, Combinatorial Analysis, Compilers, Computer Aided Design, Computer Systems Design, Functions (Mathematics), Hierarchies, Mathematical Models
Scientific paper
A Piecewise Linear (PL) network simulator called PLANET that can be used in a hierarchical design environment is presented. The most important descriptions of PL functions are compared. A method for generating a PL model automatically for an arbitrary combinatorial logic function is developed. Almost every aspect of the simulator is treated. A numerical integration method that fits in with the hierarchical structure of the simulation tree is given. The simulator is extended by a network description compiler to furnish it with a flexible interface which is almost mandatory if the simulator must be interfaced with an automatic synthesis unit. This is explained by describing a coupling with the synthesis tool. Some simulation examples are given.
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