Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

Details Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

2011-11-07

arxiv.org/abs/1111.1564v1

International Journal of Artificial Intelligence & Applications (IJAIA), Vol.2, No.3, July 2011

Computer Science

Neural and Evolutionary Computing

Scientific paper

10.5121/ijaia.2011.2302

Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequences have more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flops results more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on test patterns. This approach is time consuming and needs more efforts. Another method which is purposed in this paper is a PSO based Frame Work to optimize power dissipation. Here target is to set the entire test vector in a frame for time period 'T', so that the frame consists of all those vectors strings which not only provide high fault coverage but also arrange vectors in frame to produce minimum toggling.

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