Parasitic Effects Reduction for Wafer-Level Packaging of RF-Mems

Details Parasitic Effects Reduction for Wafer-Level Packaging of RF-Mems Parasitic Effects Reduction for Wafer-Level Packaging of RF-Mems

2007-11-21

arxiv.org/abs/0711.3275v1

Dans Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS - DTIP 2006, Stresa, Lago Maggiore : Italie (2006)

Computer Science

Other Computer Science

Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions)

Scientific paper

In RF-MEMS packaging, next to the protection of movable structures, optimization of package electrical performance plays a very important role. In this work, a wafer-level packaging process has been investigated and optimized in order to minimize electrical parasitic effects. The RF-MEMS package concept used is based on a wafer-level bonding of a capping silicon substrate to an RF-MEMS wafer. The capping silicon substrate resistivity, substrate thickness and the geometry of through-substrate electrical interconnect vias have been optimized using finite-element electromagnetic simulations (Ansoft HFSS). Test structures for electrical characterization have been designed and after their fabrication, measurement results will be compared with simulations.

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