Optimization of reversible sequential circuits

Details Optimization of reversible sequential circuits Optimization of reversible sequential circuits

2010-06-23

arxiv.org/abs/1006.4570v1

Journal of Computing, Vol. 2, No. 6, June 2010, NY, USA, ISSN 2151-9617

Computer Science

Other Computer Science

IEEE Publication Format, https://sites.google.com/site/journalofcomputing/

Scientific paper

In recent years reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardware complexity. We have designed the latches with a new reversible gate and reduced the required number of gates, garbage outputs, and delay and hardware complexity. As the number of gates and garbage outputs increase the complexity of reversible circuits, this design will significantly enhance the performance. We have proposed reversible D-latch and JK latch which are better than the existing designs available in literature.

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