Optimization of cryogenic CMOS processes for sub-10 K applications

Details Optimization of cryogenic CMOS processes for sub-10 K applications Optimization of cryogenic CMOS processes for sub-10 K applications

Jul 1992

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1992spie.1684....2g&link_type=abstract

In: Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992 (A93-53076 23-33), p. 2-39.

Computer Science

4

Cmos, Cryogenic Temperature, Field Effect Transistors, Focal Plane Devices, Optimization, Electron Mobility, Fermi Surfaces, Hysteresis

Scientific paper

Below approximately 40 K, conventional CMOS technologies show radical departures from room temperature behavior and classical theory, confounding attempts to design readout circuits that have desirable and predictable behavior. Though the effects often seem difficult to explain, they are in all cases due to the effects of carrier freezeout. We have extensively investigated the device properties of CMOS FETs at temperatures very close to absolute zero and conducted a series of process optimizations designed to overcome anomalies that dominate the device behavior. The resulting technology has been used to build readouts for very long wavelength extrinsic silicon detectors, including staring arrays of significant complexity (256 x 256 pixels). Large die sizes (450 mils) have been produced with high yields (in excess of 50 percent) using this process.

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