On-chip analog-to-digital conversion suitable for uncooled focal plane detector arrays employed in smart IR sensors

Details On-chip analog-to-digital conversion suitable for uncooled focal plane detector arrays employed in smart IR sensors On-chip analog-to-digital conversion suitable for uncooled focal plane detector arrays employed in smart IR sensors

May 1995

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1995spie.2474...72j&link_type=abstract

Proc. SPIE Vol. 2474, p. 72-87, Smart Focal Plane Arrays and Focal Plane Array Testing, Marc Wigdor; Mark A. Massie; Eds.

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This paper discusses a signal conditioning and analog-to-digital (A/D) conversion principle suitable for infrared detector arrays, especially for applications using uncooled bolometer thermal detectors. An experimental 16 X 16 array has been designed including a columnwise A/D conversion. The A/D conversion method is of general interest whenever low cost, high digital resolution, and moderate speed is desired. High resolution and linearity is obtained without trimming. The technique is similar to a sigmadelta converter, but there is no need for complex decimation filters. Row-by-row readout operation of the bolometer array is supported by the columnwise A/D conversion. The 16-column preamplifier and A/D converter structure has been implemented in a standard 0.8 micrometers CMOS process, with 40 micrometers column pitch. The resolution is expected to be 16 bits with a conversion time of 78 microsecond(s) , and the power consumption is estimated to be about 0.5 m for a single column including preamplifier and A/D conversion. MOS transistor 1/f-noise is suppressed by electrical chopping at the preamplifier input. The on-chip columnwise A/D conversion has considerable potential for smart IR cameras with on-chip bit-slice processor architectures. A flexible single chip digital camera may be achieved with the implemented structure, since the digital column data of the A/D converter array and the rows of the detector array can be selected randomly. A theoretical analysis is made of how the SNR is affected by different levels of signal conditioning parallelism. This analysis can be used for qualitative comparison between different architectures.

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