Microscale Thermal Imaging and Concurrent Thermal and Electrical Analysis of Semiconductor Devices

Computer Science – Performance

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Submicron

Scientific paper

Sub-micrometer devices found in Very Large Scale Integrated (VLSI) circuits are characterized by the presence of very high electric fields. Such high fields produce highly energetic electrons, lack of electron-phonon equilibrium and extremely high heat generation rates. Therefore, the thermal and electrical behaviors of such devices are strongly coupled. This work develops experimental techniques and theoretical models to study the thermal and electrical characteristics of sub-micrometer devices. On the experimental side, a new Scanning Thermal Imaging Microscope (STIM) based on the technology of Atomic Force Microscope (AFM) has been invented. It can be used to simultaneously obtain thermal and topographical images of sample surfaces with sub-micrometer scale spatial resolution. The STIM is particularly unique for imaging electronic components where there could be different materials and electrostatic potential variations on a scan area. Thermal images of single VLSI semiconductor devices and other components have been obtained for the first time. These images show that for a field effect transistor the hot spot occurs under the gate but on the drain side of the gate and the temperature is also a strong function of the gate voltage. It is demonstrated that this technique can be applied to semiconductor failure analysis since the failure induced hot or cold spots can be easily distinguished and located by simultaneous thermal and topographical imaging. In addition, study of heat transfer mechanism and calibration of the temperature measurement system of this new technique reveal that air heat conduction plays a major role in thermal imaging. On the theoretical side, a concurrent thermal and electrical model is developed for sub-micrometer silicon semiconductor devices by considering the non-equilibrium behavior of electrons, optical and acoustic phonons. This model includes the energy conservation equations of phonons and the well-known hydrodynamic equations of electrons. An electron Reynolds number is proposed and used to simplify the electron momentum equation. A two-dimensional numerical model is developed for a 0.4 μm gate channel length Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) on a domain consisting of a microscale region including electron and phonon transport and a macroscale region including phonon transport and interaction with the surrounding environment. Thermal effects on the device performance and reliability are calculated as decreasing electric current 14% and reducing hot electron peak temperature 18% with increase of lattice temperature 100 K. Comparison with experimental data shows the predictions of phonon temperature distributions of a field effect transistor to have the correct trend and exactly the observed asymmetric behavior with the drain side of the gate hotter than the source side.

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