MCT linear arrays and associated silicon readouts

Mathematics – Logic

Scientific paper

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Scientific paper

MCT 2×64 and 4×288 linear arrays with silicon readouts were designed, manufactured and tested. (013) MCT MBE layers were grown on GaAs substrates with ZnTe and CdTe buffer layers. 2×64 arrays were also manufactured on the base of LPE layers on CdZnTe (111) substrates. 50×55 and ≍30×30 µm area n-p-type photodiodes were formed by 50 ÷ 120 keV boron implantation. The dark currents at V ≍ 100 mV reversed biased diodes used in arrays with cutoff wavelength λco ≍ 10.0 12.2 µm were within 15 50 nA and zero bias resistance-area products were within R0A ≍ 5 ÷ 20 Ohm×cm2. Designed silicon readouts with skimming and partitioning functions were manufactured by n-channel MOS technology with buried or surface channel CCD register. For achievement with the silicon readouts the deselection function, the "composite" technology approach was considered. In this case both the technology of n-channel CCD and CMOS technology were applied, which allow to weaken considerably the technological design rules for realization of 288×4 readouts with deselection of "dead" elements. It is shown that 2.5 µm design rules for CCD and 2.0 design rules for CMOS technologies allow to realize most of the functions needed for 288×4 MCT array operation with deselection function. Before hybridisation the parameters of MCT linear arrays and Si readouts were tested separately. HgCdTe arrays and Si readouts were hybridised by cold welding In bumps technology. In dependence of FOV with skimming mode used for integration time of 8 20 µs detectivities within D*λ (0.4 1.7)×1011 cm×Hz1/2/W were achieved in dependence of the array format. Dark carrier transport mechanisms in MCT diodes were calculated and compared with experimental data.

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