Low-noise low-power readout electronics circuit development in standard CMOS technology for 4 K applications

Details Low-noise low-power readout electronics circuit development in standard CMOS technology for 4 K applications Low-noise low-power readout electronics circuit development in standard CMOS technology for 4 K applications

Jul 2006

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2006spie.6275e..38m&link_type=abstract

Millimeter and Submillimeter Detectors and Instrumentation for Astronomy III. Edited by Zmuidzinas, Jonas; Holland, Wayne S.; W

Astronomy and Astrophysics

Astronomy

3

Scientific paper

In the framework of the Photodetector Array Camera and Spectrometer (PACS) project IMEC designed the Cold Readout Electronics (CRE) for the Ge:Ga far-infrared detector array. Key specifications for this circuit were high linearity, low power consumption and low noise at an operating temperature of 4.2K. We have implemented this circuit in a standard CMOS technology which guarantees high yield and uniformity, and design portability. A drawback of this approach is the anomalous behavior of CMOS transistors at temperatures below 30-40K. These cryogenic phenomena disturb the normal functionality of commonly used circuits. We were able to overcome these problems and developed a library of digital and analog building blocks based on the modeling of cryogenic behavior, and on adapted design and layout techniques. We will present the design of the 18 channel CRE circuit, its interface with the Ge:Ga sensor, and its electrical performance. We will show how the library that was developed for PACS served as a baseline for the designs used in the Darwin-far-infrared detector array, where a cryogenic 180 channel, 30μm pitch, Readout Integrated Circuit (ROIC) for flip-chip integration was developed. Other designs and topologies for low noise and low power applications will be equally presented.

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