Key performance parameters of PLL synthesizers and an optimization method

Details Key performance parameters of PLL synthesizers and an optimization method Key performance parameters of PLL synthesizers and an optimization method

Dec 2004

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2004jtf....27..112l&link_type=abstract

Journal of Time and Frequency (ISSN 1001-1544), Vol. 27, No. 2, p. 112 - 119 (2004)

Computer Science

Performance

Phase-Locked Loop, Phase Noise, Reference Spurs

Scientific paper

The key performance parameters of PLL (Phase-Locked Loop) synthesizers,
i.e. phase noise, reference spurs and lock time, are discussed. Several
basic rules for designing a PLL synthesizer are presented. Besides, an
optimized structure is adopted to improve the performance of the
synthesizer and the feasibility is also testified by simulations.

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