Introducing a Performance Model for Bandwidth-Limited Loop Kernels

Details Introducing a Performance Model for Bandwidth-Limited Loop Kernels Introducing a Performance Model for Bandwidth-Limited Loop Kernels

2009-05-06

arxiv.org/abs/0905.0792v1

Computer Science

Performance

8 pages

Scientific paper

We present a performance model for bandwidth limited loop kernels which is founded on the analysis of modern cache based microarchitectures. This model allows an accurate performance prediction and evaluation for existing instruction codes. It provides an in-depth understanding of how performance for different memory hierarchy levels is made up. The performance of raw memory load, store and copy operations and a stream vector triad are analyzed and benchmarked on three modern x86-type quad-core architectures in order to demonstrate the capabilities of the model.

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