Computer Science – Other Computer Science
Scientific paper
2010-06-14
Journal of Computer Science and Engineering, Volume 1, Issue 1, p59-63, May 2010
Computer Science
Other Computer Science
Submitted to Journal of Computer Science and Engineering, see http://sites.google.com/site/jcseuk/volume-1-issue-1-may-2010
Scientific paper
The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, software-defined radio, wireless communication, instrumentation. In this paper, a reconfigurable FFT design using Vedic multiplier with high speed and small area is presented. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 4x4 bit multiplication operation is fragmented reconfigurable FFT modules. The 4x4 multiplication modules are implemented using small 2x2bit multipliers. Reconfigurability at run time is provided for attaining power saving. The reconfigurable FFT has been designed, optimized and implemented on an FPGA based system. This reconfigurable FFT is having the high speed and small area as compared to the conventional FFT.
Kumar Anvesh
Raman Ashish
Sarin R. K.
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