High-speed lateral PIN photodiodes in silicon technologies

Details High-speed lateral PIN photodiodes in silicon technologies High-speed lateral PIN photodiodes in silicon technologies

Jun 2004

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2004spie.5353....1s&link_type=abstract

Semiconductor Photodetectors. Edited by Linden, Kurt J.; Dereniak, Eustace L. Proceedings of the SPIE, Volume 5353, pp. 1-11

Computer Science

Performance

2

Scientific paper

High speed, efficient photodetectors are difficult to fabricate in standard silicon fabrication processes due to the long absorption length of silicon. However, high performance servers will soon require dense optical interconnects with low cost and high reliability, and this trend favors monolithic silicon receivers over hybrid counterparts. Recently, lateral PIN photodiode structures have been demonstrated in silicon CMOS technology with little or no process modifications. Optical receivers based on these detectors have achieved record performance in terms of speed and sensitivity. This paper will discuss the advantages, issues and recent advances in silicon-based photodetectors and optical receivers. This includes the fastest photodetector ever implemented in a standard bulk CMOS process, a 13.9 Gb/s lateral trench detector implemented in a modified EDRAM process, and a >15 GHz pure germanium photodiode grown directly on a silicon substrate.

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