Heterogeneous Integration, An Approach to High Density and High Flexibility Electronic Packaging

Details Heterogeneous Integration, An Approach to High Density and High Flexibility Electronic Packaging Heterogeneous Integration, An Approach to High Density and High Flexibility Electronic Packaging

Jan 2001

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2001iaop.work...23d&link_type=abstract

Forum on Innovative Approaches to Outer Planetary Exploration 2001-2020, p. 23

Computer Science

Electronic Packaging, Chips (Electronics), Spacecraft Electronic Equipment, Microelectronics, Architecture (Computers), Microelectromechanical Systems, Fault Tolerance, Integrated Circuits

Scientific paper

Key to the design of spacecraft for exploration of the outer planets will be the development of highly integrated and mass/volume efficient electronic systems. Exploration of the outer planets will require optimized propulsion approaches which mandates mass minimization. If one looks at a mission such as the Europa Lander, a high mass/volume efficiency feeds back directly into lower mass for radiation shielding. Concurrently the long mission lengths will drive the need for fault isolation and fault tolerance. The ability to build distributed electronic systems is an inherent requirement and one which is enabled by heterogeneous integration. The electronic packaging approach must be capable of interconnecting various components at a scale comparable with that on the components themselves (chip scale) and it must facilitate efficient integration of the electronics with elements of the spacecraft such as structure or antennae. The concept of 'Heterogeneous Integration' is being explored in the System On A Chip (SOAC) Project at JPL. The goal, of this approach to electronic packaging, is to enable the fabrication and assembly of complete electronic subsystems from components fabricated by a range of processes. Included in such a system could be MEMS sensors, SOI mixed signal ASICs, micro scale passive components and micro power. Secondarily the compact size will enable distributed architectures and integrated assemblies. Additional information is contained in the original extended abstract.

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