Hardening analog and power management integrated circuits against single-event effects

Details Hardening analog and power management integrated circuits against single-event effects Hardening analog and power management integrated circuits against single-event effects

Dec 2002

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2002esasp.507..265v&link_type=abstract

Proceedings of the European Space Components Conference, ESCCON 2002, 24-27 September 2002, Toulouse, France. Compiled by R.A. H

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In this paper, we review various single-event effects in analog integrated circuits which can cause system disruption or permanent damage. We also discuss a radiation-hardened fabrication process and specific part architecture, design and simulation methodologies. These capabilities have enabled the development of a line of SEE-hardened analog and power management components. The IS9- 139ASRH hardened quad comparator is used to illustrate the design methodology, and SEE data for the part is presented.

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