Computer Science – Other Computer Science
Scientific paper
2011-10-26
Computer Science
Other Computer Science
Presented in ARM Regional Engineering Conference, 2008
Scientific paper
For Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs, Cell - Based Design (CBD) is the most prevalent practice as it guarantees a shorter design cycle, minimizes errors and is easier to maintain. In modern ASIC design, standard cell methodology is practiced with sizable libraries of cells, each containing multiple implementations of the same logic functionality, in order to give the designer differing options based on area, speed or power consumption. For such library cells, thorough verification of functionality and timing is crucial for the overall success of the chip, as even a small error can prove fatal due to the repeated use of the cell in the design. Both formal and simulation based methods are being used in the industry for cell verification. We propose a method using the latter approach that generates an optimized set of test vectors for verification of sequential cells, which are guaranteed to give complete Single Input Change transition coverage with minimal redundancy. Knowledge of the cell functionality by means of the State Table is the only prerequisite of this procedure.
Nandakumar G. N.
Bhattacherjee Souvik
Bhowmick Santanu
No associations
LandOfFree
Generation of Test Vectors for Sequential Cell Verification does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.
If you have personal experience with Generation of Test Vectors for Sequential Cell Verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Generation of Test Vectors for Sequential Cell Verification will most certainly appreciate the feedback.
Profile ID: LFWR-SCP-O-718060