Focal plane array readout integrated circuit with per-pixel analog-to-digital and digital-to-analog conversion

Details Focal plane array readout integrated circuit with per-pixel analog-to-digital and digital-to-analog conversion Focal plane array readout integrated circuit with per-pixel analog-to-digital and digital-to-analog conversion

Jul 2000

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2000spie.4028..139k&link_type=abstract

Proc. SPIE Vol. 4028, p. 139-147, Infrared Detectors and Focal Plane Arrays VI, Eustace L. Dereniak; Robert E. Sampson; Eds.

Computer Science

Scientific paper

A pixel array readout integrated circuit (ROIC) containing per-pixel analog-to-digital conversion (ADC) and digital-to- analog conversion (DAC) for infrared detectors is presented with design and test result details. Fabricated in a standard 0.35 micron, 3.3 volt CMOS technology. the prototype consists of a linear array of 64 pixels, containing over 100 transistors per 30 by 30 micron pixel. The 8-bit per-pixel ADC is a Nyquist-rate single-slope design consisting of a three stage comparator and an 8 bit memory. This fully pixel- parallel ADC architecture operates in full-frame 'snapshot' mode and can reach over 1,000 frames per second. Each pixel also contains cascoded current source, globally biased to subtract an identical, fixed amount of current from each pixel in order to remove a common background signal by 'charge skimming.' It operates over more than 3 decades of current cancellation (approximately 10 pA to > 10 nA). As well, each pixel contains a 4 to 6+ bit current-mode DAC, intended to trim-out pixel-to-pixel variations in background current. It consists of 16 unit-cells of switched cascoded current sources per pixel, organized as two separately biased weights and controlled by a 16-bit per-pixel memory. The DAC operates over more than 4 decades of current cancellation (< 10 pA to approximately equals 100 nA) per least significant bit (LSB).

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