Fault tolerant computer for low Earth orbit micro satellites

Details Fault tolerant computer for low Earth orbit micro satellites Fault tolerant computer for low Earth orbit micro satellites

Nov 2004

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2004esasp.571e..58m&link_type=abstract

Proceedings of The 4S Symposium: Small Satellites, Systems and Services (ESA SP-571). 20 - 24 September 2004, La Rochelle, Franc

Computer Science

Scientific paper

This paper describes the design of the On Board Computer of Singapore's X-Sat micro satellite. The architecture incorporates the philosophies of modularity and scalability. It is based around a reliable processing core made of at least one FPGA and one microprocessor. The rest of the hardware is grouped together into functional banks using redundancy in banks for higher reliability. After the first version of the platform is validated, development effort for future missions would be substantially reduced. The computer can be reconfigured to adapt to varying mission needs, thus building a heritage with the system. The FPGA in the processing core enables transparent interfacing between heterogeneous device types when required. This combined with the modular nature of the design provides for easy upgradeability to viable technologies that become available over time. This also provides a useful platform to test out emerging devices and device types.

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