Experimental Software Schedulability Estimation For Varied Processor Frequencies

Details Experimental Software Schedulability Estimation For Varied Processor Frequencies Experimental Software Schedulability Estimation For Varied Processor Frequencies

2003-02-24

arxiv.org/abs/cs/0302033v1

Computer Science

Software Engineering

6 pages, 3 figures, published in the Proceedings of the Symposium on Software Engineering at 21th IASTED International Multi-C

Scientific paper

This paper describes a new approach to experimentally estimate the application schedulability for various processor frequencies. We use additional workload generated by an artificial high priority routine to simulate the frequency decrease of a processor. Then we estimate the schedulability of applications at different frequencies. The results of such estimation can be used to determine the frequencies and control algorithms of dynamic voltage scaling/dynamic frequency scaling (DVS/DFS) implementations. The paper presents a general problem description, the proposed schedulability estimation method, its analysis and evaluation.

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