Embedded-processor architecture for parallel DSP algorithms

Details Embedded-processor architecture for parallel DSP algorithms Embedded-processor architecture for parallel DSP algorithms

Oct 1996

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1996spie.2846...75h&link_type=abstract

Proc. SPIE Vol. 2846, p. 75-85, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, Franklin T. Luk; E

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A methodology for constructing parallel embedded DSP systems is described. The method uses a software and embedded processor abstraction to help raise the level of problem analysis above the raw state machine concept. Custom architectures are constructed by using multiple copies of a core embedded processor linked together with FIFO memories or other communication structures, and augmented with appropriate high speed data manipulation IO devices. Some field programmability and customization is possible through the use of SRAM program memories.

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