Efficient FPGA-based multipliers for F_{3^97} and F_{3^{6*97}}

Details Efficient FPGA-based multipliers for F_{3^97} and F_{3^{6*97}} Efficient FPGA-based multipliers for F_{3^97} and F_{3^{6*97}}

2007-08-22

arxiv.org/abs/0708.3022v1

Computer Science

Cryptography and Security

6 pages, 3 figures, to appear in the proceedings of FPL07

Scientific paper

In this work we present a new structure for multiplication in finite fields. This structure is based on a digit-level LFSR (Linear Feedback Shift Register) multiplier in which the area of digit-multipliers are reduced using the Karatsuba method. We compare our results with the other works in the literature for F_{3^97}. We also propose new formulas for multiplication in F_{3^{6*97}}. These new formulas reduce the number of F_{3^97}-multiplications from 18 to 15. The fields F_{3^{97}} and F_{3^{6*97}} are relevant in the context of pairing-based cryptography.

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