Dual port memory based Heapsort implementation for FPGA

Details Dual port memory based Heapsort implementation for FPGA Dual port memory based Heapsort implementation for FPGA

Jun 2011

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2011spie.8008e..13z&link_type=abstract

Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2011. Edited by Romaniuk, Ry

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This document presents a proposal of implementation of the Heapsort algorithm, which utilizes hardware features of modern Field-Programmable Gate Array (FPGA) chips, such as dual port random access memories (DP RAM), to implement efficient sorting of a data stream. The implemented sorter is able to sort one data record every two clock periods. This throughput does not depend on the capacity of the sorter (defined as number of storage cells in the sorter). The mean latency (expressed in sorting cycles - each equal to two clock periods) when sorting the stream of data is equal to the capacity of the sorter. Due to efficient use of FPGA resources (e.g. data are stored mainly in internal block RAMs), the complexity of the sorter is proportional to the logarithm of sorter capacity. Only the required RAM size is linearly proportional to the sorter capacity. The proposed sorter has been tested in simulations and synthesized for real FPGA chips to verify its correctness.

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