Design and Implementation of a Low-cost FPGA Based Delay Line Detector

Details Design and Implementation of a Low-cost FPGA Based Delay Line Detector Design and Implementation of a Low-cost FPGA Based Delay Line Detector

Dec 2008

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2008agufmsm11b1605h&link_type=abstract

American Geophysical Union, Fall Meeting 2008, abstract #SM11B-1605

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7894 Instruments And Techniques

Scientific paper

Electron spectrometers use a variety of techniques to determine where the amplified electron cloud falls onto a collecting surface. One traditional method divides the collecting surface into sectors and uses a single detector for each sector. However, as the angular and spatial resolution increases, so to do the number of detectors. Thus there is an overall increase in power consumption, cost, and weight of the detector system. An alternative approach connects each sector with a delay line and uses a pair of detectors (e.g., one at each end of the chain). To date, this technique has been implemented using Application Specific Integrated Circuits (ASICs) which are expensive to manufacture and have a long lead-time. In this paper, we report on the implementation and testing of a delay line detector using a low-cost Xilinx FPGA. Our technique is scalable to large sector numbers with very little impact on the system cost, mass, or power dissipation. The specifics of both a nine and ten sector delay system will be discussed, together with potential satellite and rocket flight applications.

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