Avionics systems on a chip for space exploration

Details Avionics systems on a chip for space exploration Avionics systems on a chip for space exploration

Jan 1999

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1999aipc..458..721a&link_type=abstract

Space technology and applications international forum -1999. AIP Conference Proceedings, Volume 458, pp. 721-728 (1999).

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Spaceborne And Space Research Instruments, Apparatus, And Components

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The advanced miniaturization of all the on-board spacecraft functions into a highly integrated, modular, and reliable architecture is a major enabling technology for future deep-space and Earth orbiting science missions. Avionics miniaturization using advanced deep sub-micron semiconductor digital, analog, as well as Micro Electro Mechanical Systems (MEMS) technologies will revolutionize the way we build future spacecraft systems. So called micro and nano satellites as well as other micro-systems are possible using these advanced technologies. In this paper, we present an overview of work in progress at the newly established JPL Center for Integrated Space Microsystems (CISM) in the area of Avionics Systems On a Chip Program. This long-term research and development program has been established as part of NASA's Advanced Deep Space Systems Program (a.k.a. X2000), which also has a near-term project-oriented element, as well as an even longer term research component called Revolutionary Computing Technologies. This paper will outline the vision, goals and scope of the SOAC program, as well as its target mission insertion opportunities. We also describe a technology roadmap from 1998 to 2006 leading to Systems On A Chip technology elements. Also described are the SOAC technology challenges and research components. The first SOAC prototype has been designed and submitted for fabrication at the MIT/LL 0.25 micron Silicon On Insulator (SOI) foundry in July 1998. It contains a telecommunications unit, power management unit, on-chip computer, non-volatile as well as volatile storage, all on a single chip. The chip will be tested at JPL in the second quarter of 1999.

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