Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs

Details Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs

1998-11-12

arxiv.org/abs/cs/9811021v1

Computer Science

Programming Languages

6 pages, 7 figures, PACT '98 Workshop on Reconfigurable Computing

Scientific paper

A high-level architecture of a Hybrid Reconfigurable CPU, based on a Philips-supported core processor, is introduced. It features the Philips XPLA2 CPLD as a reconfigurable functional unit. A compilation chain is presented, in which automatic implementation of time-critical program segments in custom hardware is performed. The entire process is transparent from the programmer's point of view. The hardware synthesis module of the chain, which translates segments of assembly code into a hardware netlist, is discussed in details. Application examples are also presented.

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