Automated Synthesis of Assertion Monitors using Visual Specifications

Details Automated Synthesis of Assertion Monitors using Visual Specifications Automated Synthesis of Assertion Monitors using Visual Specifications

2007-10-25

arxiv.org/abs/0710.4698v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Logic in Computer Science

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors from visual specifications given in CESC (Clocked Event Sequence Chart). CESC is a visual language designed for specifying system level interactions involving single and multiple clock domains. It has well-defined graphical and textual syntax and formal semantics based on synchronous language paradigm enabling formal analysis of specifications. In this paper we provide an overview of CESC language with few illustrative examples. The algorithm for automated synthesis of assertion monitors from CESC specifications is described. A few examples from standard bus protocols (OCP-IP and AMBA) are presented to demonstrate the application of monitor synthesis algorithm.

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