Computer Science – Other Computer Science
Scientific paper
2007-11-21
Dans Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS - DTIP 2006, Stresa, Lago Maggiore : Italie (2006)
Computer Science
Other Computer Science
Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions)
Scientific paper
As an alternative to the time-consuming solder pre-forms and pastes currently used, a co-electroplating method of eutectic Au-Sn alloy was used in this study. Using a co-electroplating process, it was possible to plate the Au-Sn solder directly onto a wafer at or near the eutectic composition from a single solution. Two distinct phases, Au5Sn and AuSn, were deposited at a composition of 30at.%Sn. The Au-Sn flip-chip joints were formed at 300 and 400 degrees without using any flux. In the case where the samples were reflowed at 300 degrees, only an (Au,Ni)3Sn2 IMC layer formed at the interface between the Au-Sn solder and Ni UBM. On the other hand, two IMC layers, (Au,Ni)3Sn2 and (Au,Ni)3Sn, were found at the interfaces of the samples reflowed at 400 degrees. As the reflow time increased, the thickness of the (Au,Ni)3Sn2 and (Au,Ni)3Sn IMC layers formed at the interface increased and the eutectic lamellae in the bulk solder coarsened.
Chun Sae Hwan
Jung Seung-Boo
Koo Ja-Myeong
Yoon Jeong-Won
No associations
LandOfFree
Au-SN Flip-Chip Solder Bump for Microelectronic and Optoelectronic Applications does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.
If you have personal experience with Au-SN Flip-Chip Solder Bump for Microelectronic and Optoelectronic Applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Au-SN Flip-Chip Solder Bump for Microelectronic and Optoelectronic Applications will most certainly appreciate the feedback.
Profile ID: LFWR-SCP-O-414273