Arithmetic Operations in Multi-Valued Logic

Details Arithmetic Operations in Multi-Valued Logic Arithmetic Operations in Multi-Valued Logic

2010-03-29

arxiv.org/abs/1003.5442v1

International Journal Of VLSI Design & Communication Systems 1.1 (2010) 21-32

Computer Science

Other Computer Science

12 Pages, VLSICS Journal 2010

Scientific paper

10.5121/vlsic.2010.1103

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.

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