Architectures for focal plane image processing.

Details Architectures for focal plane image processing. Architectures for focal plane image processing.

Aug 1989

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1989opten..28..865f&link_type=abstract

Opt. Eng., Vol. 28, No. 8, p. 865 - 871

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Image Processing

Scientific paper

Architectures for focal plane image processing are discussed. On-chip image preprocessing for solid-state imagers using analog CCD circuits is described for low, medium, and high density detector arrays. A spatially parallel architecture for low density, high throughput applications is described. For sparse illumination or event detection, a content-addressable architecture is proposed. A new pipelined vector pixel processor architecture for medium density infrared staring focal plane arrays is described. Neighborhood reconstruction during serial readout of high density TV-quality imagers for a pixel processor is considered using delay and analog frame memory techniques. The potential of on-chip read/write analog frame memory for image transformation and frame-to-frame processing is discussed.

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