Analysis and potentialities of backside-illuminated thinned CMOS imagers

Details Analysis and potentialities of backside-illuminated thinned CMOS imagers Analysis and potentialities of backside-illuminated thinned CMOS imagers

Feb 2004

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2004spie.5251..178m&link_type=abstract

Detectors and Associated Signal Processing. Edited by Chatard, Jean-Pierre; Dennis, Peter N. J. Proceedings of the SPIE, Volume

Computer Science

Scientific paper

CMOS imagers, now considered as a valuable alternative to CCD in many application fields, have their quantum efficiency reduced by optical filtering effects due to complex top layers structure and limited fill factor. Thinning and backside illumination (BI) have been successfully applied to CCD image sensor to improve their quantum efficiency. It can potentially be similarly applied to CMOS imagers in an attempt to allow, both the increase of impinging photons number on the photosensitive area through the suppression of top layers stack filtering, and the use of a maximal fill factor value, the whole backside surface being photosensitive. But, it has to take into account the specific features of CMOS process, mostly the limited EPI thickness in the case of the heavily doped substrate option.

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