ACS after SM4: New Life for an Old Workhorse

Computer Science – Performance

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Scientific paper

The ACS CCD Electronics Box Replacement (CEB-R) installed during SM4 features a Teledyne SIDECAR ASIC that permits optimization of the WFC via adjustment of CCD clock voltages, bias voltages, and pixel transmission timing. An on-orbit campaign to optimize the performance of the WFC was undertaken at the start of the SMOV period. Initial tests with pre-SM4 default voltages and timing patterns showed that WFC's performance matches or exceeds its pre-failure levels, notwithstanding the expected increases in dark current and hot pixels and the decline in charge-transfer efficiency due to prolonged exposure to HST's radiation environment. One WFC CCD exhibited anomalous behavior when operated with nondefault settings of its reset drain voltage. Consequently, the optimization campaign was truncated after two iterations, and ACS science operations commenced with the pre-SM4 default configuration. Several artifacts attributed to the CEB-R appear in post-SM4 WFC images: large-scale but stable bias gradients, low-level but temporally variable horizontal stripes, a signal-dependent bias shift, and amplifier crosstalk. STScI has developed algorithms for the correction or mitigation of these electronic artifacts as well as for the restoration of images affected by continuously degrading CTE. Standalone correction packages are now or will soon be publicly available. These packages will be incorporated into the calacs package of the OPUS data pipeline by September 2011.

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