A polynomial-time heuristic for Circuit-SAT

Details A polynomial-time heuristic for Circuit-SAT A polynomial-time heuristic for Circuit-SAT

2005-11-18

arxiv.org/abs/cs/0511071v4

Computer Science

Computational Complexity

20 pages, 8 figures

Scientific paper

In this paper is presented an heuristic that, in polynomial time and space in
the input dimension, determines if a circuit describes a tautology or a
contradiction. If the circuit is neither a tautology nor a contradiction, then
the heuristic finds an assignment to the circuit inputs such that the circuit
is satisfied.

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