A digital phase-shifting frequency-dividing clock designed with CPLD

Details A digital phase-shifting frequency-dividing clock designed with CPLD A digital phase-shifting frequency-dividing clock designed with CPLD

Jun 2004

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2004jtf....27....1y&link_type=abstract

Journal of Time and Frequency (ISSN 1001-1544), Vol. 27, No. 1, p. 1 - 7 (2004)

Mathematics

Logic

Complex Programmable Logic Device (Cpld), Digital Phase-Shifting Frequency-Dividing Clock

Scientific paper

A digital phase-shifting frequency-dividing clock has been designed with CPLD (Complex Programmable Logic Device) technique which modularizes hardware circuit and integrates different modules into one chip. Compared with original circuit designed with separate components this design is characterized by simple hardware circuit and high reliability, and is easy to be debugged.

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