Computer Science – Performance
Scientific paper
Dec 1991
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1991spie.1540..285s&link_type=abstract
Proc. SPIE Vol. 1540, p. 285-296, Infrared Technology XVII, Bjorn F. Andresen; Marija S. Scholl; Irving J. Spiro; Eds.
Computer Science
Performance
Scientific paper
The design of a 1st and 2nd generation 640(H) X 480(V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. Measured performance characteristics for Gen 1 devices are presented along with calculated performance for the Gen 2 design. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non- interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS170 operation) resulting in a form of 'electronic shutter,' or variable exposure control. The pixel size of 24-micrometers X 24-micrometers results in a fill factor of 38% for 1.5-micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.
Esposito Benjamin J.
Gilmartin Harvey R.
Hseuh Fu-Lung
Levine Peter A.
Meray Grazyna M.
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