10-GOPS transversal filter and error table compensator

Details 10-GOPS transversal filter and error table compensator 10-GOPS transversal filter and error table compensator

Nov 1999

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1999spie.3807..157b&link_type=abstract

Proc. SPIE Vol. 3807, p. 157-163, Advanced Signal Processing Algorithms, Architectures, and Implementations IX, Franklin T. Luk;

Computer Science

Scientific paper

A cascadable 10GOPS transversal filter chip has been designed and fabricated and can operate in 32-tap symmetric, 32-tap anti- symmetric or 16-tap non-symmetric modes. It has programmable tap weights and uses 16-bit signed arithmetic with radix-16 multipliers and 4 - 2 compressors to reduce the transistor count. The chip was fabricated in a 0.35 micrometer CMOS process, measures 3.1 X 4.4 mm and contains 310,000 transistors. The chip is pipelined and has a maximum clock rate of 200 MHz (200 MSa/s throughput). An error table compensator system using a lookup table has been built using the transversal filter programmed as a wideband differentiator with some additional on chip circuits including delays and an adder. An external memory stores the error table. The error table technique is capable of providing between 7 to 15 dB improvement in the dynamic range of typical 100 Ms/s A/D converters. An application to pulse shaping of high chip rate spread spectrum signals is also discussed.

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