0-level Vacuum Packaging RT Process for MEMS Resonators

Details 0-level Vacuum Packaging RT Process for MEMS Resonators 0-level Vacuum Packaging RT Process for MEMS Resonators

2008-02-21

arxiv.org/abs/0802.3093v1

Dans Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS - DTIP 2007, Stresa, lago Maggiore : Italie (2007)

Computer Science

Other Computer Science

Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/EDA-Publishing)

Scientific paper

A new Room Temperature (RT) 0-level vacuum package is demonstrated in this work, using amorphous silicon (aSi) as sacrificial layer and SiO2 as structural layer. The process is compatible with most of MEMS resonators and Resonant Suspended-Gate MOSFET [1] fabrication processes. This paper presents a study on the influence of releasing hole dimensions on the releasing time and hole clogging. It discusses mass production compatibility in terms of packaging stress during back-end plastic injection process. The packaging is done at room temperature making it fully compatible with IC-processed wafers and avoiding any subsequent degradation of the active devices.

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