Computer Science – Performance
Scientific paper
Mar 2005
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2005spie.5730..261z&link_type=abstract
Optoelectronic Integration on Silicon II. Edited by Kubby, Joel A.; Jabbour, Ghassan E. Proceedings of the SPIE, Volume 5730
Computer Science
Performance
Scientific paper
This work describes a dual-rate optical transceiver designed for power-efficient connections within and between modern high-speed digital systems. The transceiver can dynamically adjust its data rate according to the performance requirements, allowing for power-on-demand operation. To implement dual rate functionality, the transmitter and receiver circuits include separate high-speed and low-power datapath modules. The high-speed module is designed for gigabit operation and optimized to achieve the maximum bandwidth. A simpler low-power module is designed for megabit data transmission and optimized for low power consumption. The transceiver was fabricated with a 0.5μm Silicon-on-Sapphire (SOS) CMOS technology. The vertical cavity surface-emitting lasers (VCSELs) and photodetector devices were attached to the transceiver IC using flip-chip bonding. A free-space optical link system was set up to demonstrate power-on-demand capability. Experimental results show reliable link operations at 2Gb/s and 100Mb/s data transfer rates with about 104mW and 9mW power consumption, respectively. The transceiver"s switching time between these two data rates was demonstrated at 10μs which was limited by on-chip register reconfiguration time. Improvement of this switching time can be obtained by using dedicated IO pads for dual-rate control signals. At the circuit level, the incorporation of dual rate functionality into a typical gigabit optical transceiver would require 255 additional MOS transistors.
Ekman Jeremy
Gui Ping
Haney Michael
Kiamilev Fouad
McFadden Michael
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